1. Field of the Invention
The invention relates to a radiation hardened programmable phase frequency divider for implementation in deep submicron CMOS technology, and particularly to a design structure embodied in a machine readable medium for designing, manufacturing and/or testing the radiation hardened programmable phase frequency divider circuit.
2. Background Information
CMOS circuits used in space applications are subject to single event upsets (SEU's) as a result of exposure to radiation consisting of alpha particles or neutrons. The charge induced by a single SEU hit can be as high as 1 picoCoulomb (pC), and can have a 2 miliAmpere (mA) amplitude with a 1 nanosecond (ns) period. When a programmable phase frequency divider (PPFD) used in such a space application is running at a frequency lower than 200 Megahertz (MHz), an SEU hit with 1 pC charge may not always cause a soft error if the timing of the SEU does not fall within the window for the set and hold times of any of the flip flops in the PPFD. In such case, a dual interlocked cell (DICE) type flip flop design, such as the one described in Weizhong Wang and Haiyan Gong, “Sense Amplifier Based RADHARD Flip Flop Design,” IEEE Transactions on Nuclear Science, Vol. 51, No. 6 (December 2004), may be used. However, a PPFD fabricated in deep micron technology can run at frequencies in the Gigahertz (GHZ) range. In this case, the vulnerable timing window for set and hold of the PPFD's D-type flip flops (DFF's) will always be covered by the typical 1 ns period of an SEU hit. Under these circumstances, what is required is an innovative radiation hardening technique to ensure that the PPFD continues to function properly in a radiation environment.